From: "John McKown" <[email protected]> Sent: Tuesday, 7 September 2010 6:01 AM
Funny, to me, is that RISC was supposed to be the wave of the future (way back when) due to simpler and faster hardware
That was vogue when the capabilities of microprocessors were somewhat limited. The difficulty with that idea is that the processor needs to run some 10 times faster than CISC in order to achieve similar speeds. With CISC instructions such as TR, ED, etc, the benefits can be seen of doing a decent unit of well-planned work. The same task using discrete instructions (IC, A, C, etc) takes about 5 to 10 times as long and requires a much longer instruction stream. Fetching those instructions ties up memory with addresses that not only conflict with addresses of the data ; they also use up bandwidth to memory. With the operations spelled out in microcode, most of the arithmetic and house-keeping tasks are performed in the hardware microcode processor, they don't tie up user registers, and the only memory access requirements are those required to fetch and store data bytes.
with smarter compilers. Instead, we seem to have put the complexity into hardware instead of the compiler. Hum, does this mean that the compiler writers are not as smart as the hardware designers? <grin type="crooked"/> The same with the new 3 operand instructions which basically implement A=B+C. I would guess this is also to support the compiler writers so that they can reserve a register over a number of instructions more easily. I'm not a compiler writer, so this is a guess. Eg. to make it easier to compile efficient code such as: A=B+1 C=B+D E=B*3 With 2 operand instructions, the variable B would need to be reloaded 3 times. With 2 operand instructions, only once.
That is self-contradictory. Do you mean 3-operand instructons?
