The PSW has two bits which, together, indicate the AMODE. They are the EA bit, 
bit 31. And the BA bit, bit 32. Now, the PoPS clearly states that having the EA 
bit ON and the BA bit OFF is invalid and causes a "specification exception" to 
be raised. Now, I don't know how the hardware works. But one reason that I can 
think of as why the ON/OFF combo is invalid is due to how the hardware tests 
for the current AMODE. If it first tests the BA bit for '0'b to see if the 
AMODE is 24, then if would make sense to require the EA bit to be OFF in this 
case as it would not be tested. So they made it required for completeness. IE, 
hardware AMODE is determined somewhat like:

IF BA=0 THEN AMODE=24 ELSE IF EA=0 THEN AMODE=31 ELSE AMODE=64

This would test the AMODE in order of their evolution in the hardware. An 
alternate evaluation could be:

IF EA=1 THEN AMODE=64 ELSE IF BA=0 THEN AMODE=24 ELSE AMODE=31

Anyway, strickly for the purposes of speculation, what sort of addressing mode 
could a future z architecture make up which would use EA=1 BA=0? And how much 
overhead in the hardware would it cost? it would cost because we don't 
currently need to test EA if BA is 0 by the first scenario or to test BA if EA 
is 1 in the second.

Or maybe I should just take another pain pill and go to the rest of the way to 
sleep.

John McKown
Systems Engineer IV
IT

Administrative Services Group

HealthMarkets(r)

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