On 21 June 2011 11:13, Farley, Peter x23353 <[email protected]> wrote:
>> > Yes, that is certainly part of it, though not the whole of it. The link >> > you provided shows all of the current z/Arch and even 360-era >> > instructions plus some others I was not even aware of in the assist >> > category, thanks! But that page doesn't show the machine level at which >> > an instruction (or more generally the facility that contains the >> > instruction) became available. >> >> Yes it does. http://www.tachyonsoft.com/inst390m.htm > > I missed the links at the bottom of that page. Thanks again, that is very > helpful, just what I needed. Slightly off topic, but something that came up not long ago on another list is that of opcodes reserved for causing an operation exception. It is very interesting to compare the wording from the current zArch Principles of Operation: Programming Notes: 1. Some models may offer instructions not described in this publication, such as those provided for assists or as part of special or custom features. Consequently, operation codes not described in this publication do not necessarily cause an operation exception to be recognized. Furthermore, these instructions may cause modes of operation to be set up or may otherwise alter the machine so as to affect the execution of subsequent instructions. To avoid causing such an operation, an instruction with an operation code not described in this publication should be executed only when the specific function associated with the operation code is desired. 2. Operation code 00 hex will never be assigned to an instruction implemented in the CPU to that in the S/370 Principles of Operation (in this case GA22-7000-4 from 1975): 1. Some models may offer instructions not listed in this manual, such as those provided for emulation or as part of special or custom features. Consequently, all unlisted operation codes do not necessarily cause an operation exception to be recognized. Furthermore, as part of the specified operation, these instructions may cause modes of operation to be set up or otherwise alter the system so as to affect the execution of subsequent instructions. In order to avoid the possibility of accidently causing such operation, instructions with an unlisted operation code should be issued only when the specific function associated with the operation code is desired. 2. The operation code 00, with a two-byte instruction format, and the set of sixteen 16-bit operation codes B2E0 to B2EF, with a four-byte instruction format, are allocated for software uses where indication of invalid operation is required. It is improbable that these operation codes will ever be assigned to an instruction implemented in the CPU. I find it a bit sad that, even though IBM's "improbable" has become "never" in the case of opcode 00, it has recently become "in use" for several of the B2Ex series. When did this doc change happen? With XA I'd guess, but I don't have the books here. I suppose it's a bit late to send an RCF to either book. The last time I sent one for the S/370 book, fittingly, to P/O Box 390, Poughkeepsie, NY, it was returned "address unknown", like the once common S0C5 abend. Tony H.
