L1 cache should keep up with the processor. It is 128K or 512 lines of L1
cache, so if the data you are working on will fit in L1 and not roll it, then
that should not be your problem.
L1.5 is about 8 times slower than L1, if memory serves me correctly.
The other thing to consider is the super scalier nature of a z10 and z196. The
machine wants to process 2 or 3 instructions in the same cycle if they are not
dependent on each other. If instruction #2 is dependent on instruction #1,
then #2 gets held until #1 completes. It gets even more complicated. If #2 is
just using in a register what #1 produced there is a delay of 3 or 4 cycles,
but if #2 is using what #1 produced as part of an address, the delay can be
like 8 or 9 cycles.
Examples
L R1,data
AHI R1,1 delay 3/4 cycles
....
LA R1,structure
L R2,20(,R1) delay 8/9 cycles
I don't know what the delays are for MVC type instructions that reference the
same memory. Does anyone on the list know? Best open reference that I know of
is the Bob Rodgers presentation at SHARE, How Do You Do What You Do When You
Are A z10?
Christopher Y. Blaicher
Senior Software Developer
Austin Development Lab
phone: 512.340.6154
mobile: 512.627.3803
fax: 512.340.6647
10431 Morado Circle
Austin, TX 78759
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:[email protected]] On
Behalf Of Fred van der Windt
Sent: Monday, August 15, 2011 6:23 AM
To: [email protected]
Subject: Re: Pipeline question
> >> memory accesses are killing you.
>
> I do everything in less than 1K (plus TR-tables read) so....
I remember a document that listed the latencies of the various z196 caches but
I can't find it anymore. That should give us some idea of the cost of loading
and storing data versus 'keeping it in the processor'.
Maybe somebody else knows if this information is available somewhere?
Fred!
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