On 17 January 2012 08:09, Fred van der Windt <[email protected]> wrote:
> I did a very Q&D test and... > > J *+10 > CLC 0(1,R10),8(R10) > EXRL R1,*-6 > > ...is about 25% faster than... > > CLC 0(1,R10),8(R10) > EXRL R1,*-6 > > So on a z196 the jump seems to be faster than the compare... This seems unsurprising. Even on much older processors, an unconditional branch has been predicted as "taken", and so the instruction stream fetching will be at the EXRL long before execution gets to the J. If R1 was set some instructions earlier, the EXRL and target CLC can be set up and ready to go way in advance. Tony H.
