The second quoted information is exactly what I was asking for. Thanks, Jon.
________________________________ From: "McKown, John" <[email protected]> To: [email protected] Sent: Thu, May 24, 2012 9:05:54 AM Subject: Re: MVC with 2nd operand length You are probably thinking of this: <quote> The execution of the instruction is interruptible. When an interruption occurs, other than one that follows termination, the lengths in general registers R1 + 1 and R2 + 1 are decremented by the number of bytes moved, and the addresses in general registers R1 and R2 are incremented by the same number, so that the instruction, when reexecuted, resumes at the point of interruption. In the 24-bit or 31-bit addressing mode, the leftmost bits which are not part of the address in bit positions 32-63 of general registers R1 and R2 are set to zeros, and the contents of bit positions 0-31 remain unchanged. In any addressing mode, the contents of bit positions 0-39 of general registers R1 + 1 and R2 + 1 remain unchanged; and the condition code is unpredictable. If the operation is interrupted during padding, the length field in general register R2 + 1 is 0, the address in general register R2 is incremented by the original length in general register R2 + 1, and general registers R1 and! R1 + 1 reflect the extent of the padding operation. </quote> in http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR003/7.5.90 However, you need also to refer here: http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR003/5.3.6.3 <quote> Completion: On completion of the last unit of operation of an interruptible instruction, the instruction address in the old PSW designates the next sequential instruction. The result location for the current unit of operation has been updated. It depends on the particular instruction how the operand parameters are adjusted. On completion of a unit of operation other than the last one, the instruction address in the old PSW designates the interrupted instruction or an EXECUTE instruction, as appropriate. The result location for the current unit of operation has been updated. The operand parameters are adjusted such that the execution of the interrupted instruction is resumed from the point of interruption when the old PSW stored during the interruption is made the current PSW. </quote> So, if it is interrupted, the registers and storage have been updated. But the PSW continues to point to the interrupted instruction, not to the next instruction. z/OS saves the interrupt PSW appropriately, and when it redispatches the unit of work, the PSW points to the incomplete MVCL and thus it is reissued "automatically". Of course, this does assume that nothing in the interim messes around with the areas where the registers and PSW are stored. -- John McKown Systems Engineer IV IT Administrative Services Group HealthMarkets(r) 9151 Boulevard 26 * N. Richland Hills * TX 76010 (817) 255-3225 phone * [email protected] * www.HealthMarkets.com Confidentiality Notice: This e-mail message may contain confidential or proprietary information. If you are not the intended recipient, please contact the sender by reply e-mail and destroy all copies of the original message. HealthMarkets(r) is the brand name for products underwritten and issued by the insurance subsidiaries of HealthMarkets, Inc. -The Chesapeake Life Insurance Company(r), Mid-West National Life Insurance Company of TennesseeSM and The MEGA Life and Health Insurance Company.SM > -----Original Message----- > From: IBM Mainframe Assembler List > [mailto:[email protected]] On Behalf Of Jon Perryman > Sent: Thursday, May 24, 2012 10:35 AM > To: [email protected] > Subject: Re: MVC with 2nd operand length > > Has anyone from IBM endorsed this? POP's doesn't state that the PSW is > decremented to cause re-execution of the instruction. > > Thanks, Jon. > > > > ________________________________ > From: Paul Gilmartin <[email protected]> > To: [email protected] > Sent: Wed, May 23, 2012 9:37:23 PM > Subject: Re: MVC with 2nd operand length > > On May 23, 2012, at 22:27, Jon Perryman wrote: > > > MVCL is an instruction begging for a macro. Besides loading > registers and > > destroying the contents of 4 registers upon completion, it is also > >interruptible > > so you have to ensure the move is complete. > > > Ensuring the move is complete is handled by the hardware. > > -- gil > >
