The assembler always places generated instructions on a 1/2 wd boundary. Labels generated using DS 0H or DC 0H are always placed on a 1/2 wd boundary. Labels generated using EQU * are placed at the current value of the instruction counter. That is why using EQU * is risky for labels in code. Murphy says probability of an S0C1 should be 50% but it is usually higher.
IBM Mainframe Assembler List <[email protected]> wrote on 06/13/2012 11:31:33 AM: > From: Doron Geva <[email protected]> > So can assembler issue a message (error) when an instruction is not on a > half word boundary and old BRANCH (not relative/long displacment BRANCH) is > also not a half word boundary? ----------------------------------------- The information contained in this communication (including any attachments hereto) is confidential and is intended solely for the personal and confidential use of the individual or entity to whom it is addressed. If the reader of this message is not the intended recipient or an agent responsible for delivering it to the intended recipient, you are hereby notified that you have received this communication in error and that any review, dissemination, copying, or unauthorized use of this information, or the taking of any action in reliance on the contents of this information is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail, and delete the original message. Thank you
