http://www.anandtech.com/show/6290/making-sense-of-intel-haswell-transactional-synchronization-extensions
<quote from second page>
The new Transactional Synchronization eXtensions (TSX) extend the x86 ISA with 
two new interfaces: HLE and RTM.

Restricted Transactional Memory (RTM) uses Xbegin and Xend, allowing developers 
to mark the start and end of a critical section. The CPU will thread this piece 
of code as an atomic transaction. Xbegin also specifies a fall back path in 
case the transaction fails. Either everything goes well and the code runs 
without any lock, or the shared variable(s) that the thread is working on is 
overwritten. In that case, the code is aborted and the transaction has failed. 
The CPU will now execute the fall back path, which is most likely a piece of 
code that does coarse grained locking. RTM enabled software will only run on 
Haswell and is thus not backwards compatible, so it might take a while before 
this form of Hardware Transactional Memory is adopted.

The most interesting interface in the short term is Hardware Lock Elision or 
HLE. It first appeared in a paper by Ravi Rajwar and James Goodman in 2001. 
Ravi is now a CPU architect at Intel and presented TSX together with his 
colleague Martin Dixon TSX at IDF2012.

The idea is to remove the locks and let the CPU worry about consistency. 
Instead of assuming that a thread should always protect the shared data from 
other threads, you optimistically assume that the other threads will not 
overwrite the variables that the thread is working on (in the critical 
section). If another thread overwrites one of those shared variables anyway, 
the whole process will be aborted by the CPU, and the transaction will be 
re-executed but with a traditional lock.
</quote>

--
John McKown
Systems Engineer IV
IT

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