The two newest processors (z196 and zEC12) do out-of-order processing. Does that mean that we do not need to 'intermingle' instructions because the processor will do it for us?
Fred! Sent from my new iPad On Apr 18, 2013, at 17:05, "Phil Smith III" <[email protected]> wrote: > John Ehrman wrote: >> Performance concerns about individual instructions aren't worth much >> effort. Things like operand alignment, data and instruction cache >> retention, locality of reference, branch frequency etc. can have really >> significant effects. > > For sure. But for the pathologically curious, if you have z/VM source, look > at the main module for EXEC 2 (DMSEXE). It's full of lines like: > SLR R0,R8 (DO IT WHILE R3 SETTLES) > > These must go back to what, 303x? 370 itself? Christopher J. Stephenson Sir > Chris the EXECutor) wrote this code 30+ years ago, when that stuff DID > matter. > > There were giants in those days...! > > ...phsiii ----------------------------------------------------------------- ATTENTION: The information in this electronic mail message is private and confidential, and only intended for the addressee. Should you receive this message by mistake, you are hereby notified that any disclosure, reproduction, distribution or use of this message is strictly prohibited. Please inform the sender by reply transmission and delete the message without copying or opening it. Messages and attachments are scanned for all viruses known. If this message contains password-protected attachments, the files have NOT been scanned for viruses by the ING mail domain. Always scan attachments before opening them. -----------------------------------------------------------------
