The instructions mentioned work the same in AMODE 31 as in AMODE 64, at least
in terms of work done. The difference is in addressing mode. LGR loads 64
bits from one register to another, regardless of the addressing mode. LMG and
STMG also load and store 64 bit registers from/to memory. For these
instructions the only difference brought on by AMODE is in the addresses used.
One thing that many don't think about is locality of reference. The machine I
work on is a Z12 with the following cache structure.
LEVEL 1 CACHE EXISTS
LEVEL 1 CACHE IS PRIVATE TO THIS PROCESSOR
LEVEL 1 CACHE HAS INSTRUCTION AND DATA CACHES
LEVEL 1 DATA CACHE LINE SIZE IS . . . . . . . . 256
LEVEL 1 TOTAL DATA CACHE SIZE IS. . . . . . . . 96K
LEVEL 1 DATA CACHE SET ASSOCIATIVITY IS . . . . 6
LEVEL 1 INSTRUCTION CACHE LINE SIZE IS . . . . 256
LEVEL 1 TOTAL INSTRUCTION CACHE SIZE IS . . . . 64K
LEVEL 1 INSTRUCTION CACHE SET ASSOCIATIVITY IS 4
LEVEL 2 CACHE EXISTS
LEVEL 2 CACHE IS PRIVATE TO THIS PROCESSOR
LEVEL 2 CACHE HAS INSTRUCTION AND DATA CACHES
LEVEL 2 DATA CACHE LINE SIZE IS . . . . . . . . 256
LEVEL 2 TOTAL DATA CACHE SIZE IS. . . . . . . . 1,024K
LEVEL 2 DATA CACHE SET ASSOCIATIVITY IS . . . . 8
LEVEL 2 INSTRUCTION CACHE LINE SIZE IS . . . . 256
LEVEL 2 TOTAL INSTRUCTION CACHE SIZE IS . . . . 1,024K
LEVEL 2 INSTRUCTION CACHE SET ASSOCIATIVITY IS 8
LEVEL 3 CACHE EXISTS
LEVEL 3 CACHE IS SHARED BETWEEN PROCESSORS
LEVEL 3 CACHE IS A UNIFIED CACHE
LEVEL 3 UNIFIED CACHE LINE SIZE IS . . . . . . 256
LEVEL 3 TOTAL UNIFIED CACHE SIZE IS . . . . . . 49,152K
LEVEL 3 UNIFIED CACHE SET ASSOCIATIVITY IS . . 12
LEVEL 4 CACHE EXISTS
LEVEL 4 CACHE IS SHARED BETWEEN PROCESSORS
LEVEL 4 CACHE IS A UNIFIED CACHE
LEVEL 4 UNIFIED CACHE LINE SIZE IS . . . . . . 256
LEVEL 4 TOTAL UNIFIED CACHE SIZE IS . . . . . . 393,216K
LEVEL 4 UNIFIED CACHE SET ASSOCIATIVITY IS . . 24
Once you exceed the capacity of level 1 cache, you will start to get a
performance hit. Exceed the capacity of the level 2 cache and it just gets
worse, faster.
Question: Did you go to 64-bit storage to hold a larger table? Is your access
to it now more random so that now you are rolling cache or rolling more levels
of cache?
Chris Blaicher
Technical Architect
Software Development
Syncsort Incorporated
50 Tice Boulevard, Woodcliff Lake, NJ 07677
P: 201-930-8234 | M: 512-627-3803
E: [email protected]
-----Original Message-----
From: IBM Mainframe Assembler List [mailto:[email protected]] On
Behalf Of Brite
Sent: Tuesday, May 05, 2015 9:36 AM
To: MVS List Server 2
Subject: Re: LNKEDT 64-bit mode assembler in AMODE 31
I compared to the performance of same programs before they were converted to
64-bit. How do those 64-bit instructions (e.g. LGR, STMG, LMG) work in 31-bit
AMODE? This is the first I have to deal with 64-bit mode.
