First, it shouldn't take more time to write the macro you want than it did the email :-)
Second, I'm not sure there's any benefit in differentiating 32 vs. 64 bit regs. There *are* the same, of course. Also, I believe HLASM flags some instructions incorrectly (iirc, it requires GR32 for LLILL, or GR64 for IILL). Third, I believe that MVI example would be flagged as improper, but I'm pretty sure no one's going to "enhance" HLASM to evaluate comments. Fourth (I really don't know why I'm numbering my paragraphs today), too many programmers aren't nearly anal enough :-) sas > -----Original Message----- > > From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@ > LISTSERV.UGA.EDU] > > On Behalf Of John McKown > > Sent: 20 July 2017 20:52 > > To: [email protected] > > Subject: superior IBM supplied "register equate" macro? > > > > I know about YREGS and IAZYREG. But there are not what I want. What I > want > > would have lines akin to: > > > > R0 EQU 0,,,,GR > > R0_64 EQU 0,,,,GR64 > > R0_32 EQU 0,,,,GR32 > > AR0 EQU 0,,,,AR > > > > > > ​Am I just being "too anal" in wanting to have something flagged like: > > > > MVI SOMEVAR,R0 SAVE HIGH BYTE OF R0 IN STORAGE > > * ABOVE COMMENT IS OBVIOUSLY DONE BY A ROOKIE > > > > or > > > > LG R0,DOUBLEWORD​ > > > > >
