Is this one of those situations that is controlled by a control register bit? VM does not interpret every instruction like Hercules. It must be getting an interrupt on STFLE or whatever.
Charles -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Tom Marchant Sent: Thursday, March 28, 2019 11:48 AM To: [email protected] Subject: Re: Determing the Presence of an Instruction On Thu, 28 Mar 2019 09:56:23 -0700, Charles Mills wrote: >VM does a fair amount of "interception" and instruction simulation in any >event. For privileged instructions, yes. In this case, something has to happen for non-privileged instructions too. -- Tom Marchant > >-----Original Message----- >From: IBM Mainframe Assembler List [mailto:[email protected]] On >Behalf Of Tom Marchant >Sent: Thursday, March 28, 2019 9:37 AM >To: [email protected] >Subject: Re: Determing the Presence of an Instruction > >On Thu, 28 Mar 2019 11:07:34 -0400, Tony Thigpen wrote: > >>You define relocation domains that may contain all or just some of the >>different processors available. The directory entry can state which >>domain the guest is to use. >> >>z/VM automatically determines the lowest common facilities within each >>relocation domain. >> >>When the guest signs on and IPL's, since z/VM already knows what the >>lowest common facilities are available, it automatically tells the guest >>such when the guest issues the STFLE instruction. z/VM also modifies the >>results for other 'query' type functions, such as KM, to only return the >>lowest common value. >> >>So, yes, it is fairly automatic. The z/VM programmers did a really good >>job on this. > >z/VM also has to tell the processor, every time a guest is dispatched on >that processor, what facilities it is to process, or which it is to pretend >do not exist. So that if the guest issues an instruction that was >introduced on a z14 after zVM told it that it was to behave like a z12, >a PIC 1 would occur. > >The processor would have to be given this information every time a >guest that was running on a different emulated level of hardware was >dispatched on that processor. And, of course, at any given moment, >different processors might be running at different levels. > >If a spare CP was switched in by the hardware to handle an error, that >information would have to be transferred as well. > >It seems like there would be a fair amount of overhead in this. Still, it >is an intriguing capability. > >-- >Tom Marchant
