Actually, the PoO is fairly verbose about this ... it's a particular model's implementation which may be fuzzy. On page 7-39 RHC, the last paragraph of the instruction description states:
It is model dependent whether an access exception or PER zero-address-detection event is recognized for the second operand when the condition code in the current PSW designates a bit position in the M1 field containing a zero. So, the instruction may actually attempt to fetch the second-operand storage location, even though it is not needed. This may not seem to be the ideal scenario, but it affords the hardware designer some flexibility in speeding up the implementation. Avoiding the need for an intermediate register is BIC's raison d'être.
