With the new COBOL compilers capable of generating vector instructions for handling packed fields, I'm looking at modifying our ESTAE routines to dump the contents of the vector registers. The PoOPs says you should not issue a vector instruction unless both the vector enablement control and AFP-register control bits in CR0 are on. If you're running z/OS on a z13 of higher (i.e. your machine a vector instruction support), would either of these two bits ever be off?
>From a standard ESTAE routine, I can examine the CR0 contents from the SDWA, >but in a CICS ABEND exit, I don't have access to CR0. Robert Ngan HCL Technologies P.S. Is there a mapping macro for the control register bit flags? DXC Technology Company - Headquarters: 1775 Tysons Boulevard, Tysons, Virginia 22102, USA. DXC Technology Company -- This message is transmitted to you by or on behalf of DXC Technology Company or one of its affiliates. It is intended exclusively for the addressee. The substance of this message, along with any attachments, may contain proprietary, confidential or privileged information or information that is otherwise legally exempt from disclosure. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate any part of this message. If you have received this message in error, please destroy and delete all copies and notify the sender by return e-mail. Regardless of content, this e-mail shall not operate to bind DXC Technology Company or any of its affiliates to any order or other contract unless pursuant to explicit written agreement or government initiative expressly permitting the use of e-mail for such purpose.
