On Thu, 3 Sep 2020 21:19:12 +0000 Keven <[email protected]> wrote:
:> Couple of things... :>1) In MVS et. al., what characteristics differentiate a First-Level Interrupt Handler from a Second-Level Interrupt Handler? Is the transition from FLIH to SLIH determined by say, a state change due to LPSW/E? Maybe transitioning from first-level to second-level is indicative of the interrupted dispatchable-units state data having been copied to its own control blocks (TCB/RB, SRB etc.) from the processors (PSA, LCCA/PCCA etc.)? Basic difference is that the FLIH gets control in an unknown environment and is responsible to verify that the environment is supported and then save status to allow the real interrupt handler to get control. :>2) When IBM S/370 engineers decided that, okay maybe 16MiB of addressable storage isnt enough after all but theres no way yall will ever need 4-GiB (I mean, cmon) so were making our new XA architecture with a (31-bit) 2-GiB address space, I wonder, had they instead made XA a 32-bit system would that mean that z/Architecture would have to be limited to 63-bits in order to provide compatibility between (what would have been) 32-bit 390/ESA and 63-bit z/Architecture in a manner analogous to how compatibility between 24-bit S/370 and 31-bit 370/XA systems was implemented? Would (24, 32, 63) have been a better bit-size expansion sequence than was (24, 31, 64)? Don't have a clue as to what you are suggesting. -- Binyamin Dissen <[email protected]> http://www.dissensoftware.com Director, Dissen Software, Bar & Grill - Israel Should you use the mailblocks package and expect a response from me, you should preauthorize the dissensoftware.com domain. I very rarely bother responding to challenge/response systems, especially those from irresponsible companies.
