A cache line is 256 bytes. If the code that modifies an instruction is in the same cache line as the instruction, then multiple cache line refreshes have to happen. The cache line for the modified instruction has to be brought into the data cache and modified. This causes the cache line in the instruction cache to be invalidated. The cache line then has to be refreshed into the instruction cache and then the next instruction re-fetched. Doing an EX causes no cache line refreshes and does not interfere with the pipeline. As I said, EX has its own set of overheads, but are a very small fraction of modifying an instruction.
Chris Blaicher Technical Architect Precisely.com -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Farley, Peter x23353 Sent: Monday, October 26, 2020 2:33 PM To: [email protected] Subject: Re: Is TESTCB a bad boy ? This message originated Externally. Use proper judgement and caution with attachments, links, or responses. Isn't that true only if the dynamically built instruction isn't in the same cache line as the code that performs the build and EX? I've seen examples where the "built" instruction was a non-reentrant location in the same CSECT and very near to the "build" instructions. Not my code, but I have seen it. Peter -----Original Message----- From: IBM Mainframe Assembler List <[email protected]> On Behalf Of Christopher Y. Blaicher Sent: Monday, October 26, 2020 2:07 PM To: [email protected] Subject: Re: Is TESTCB a bad boy ? This will not have the same performance hit. The problem with the MVI was the CPU had to 1) bring the cache line into the data cache; 2) apply the MVI data; 3) refresh the cache line in the instruction cache; and finally 4) execute the instruction. Doing an EX skips steps 1, 2 and 3. EX has its own set of overheads, but nowhere near what all the cache hits have. Chris Blaicher Technical Architect Precisely.com -----Original Message----- From: IBM Mainframe Assembler List [mailto:[email protected]] On Behalf Of Melvyn Maltz Sent: Monday, October 26, 2020 11:16 AM To: [email protected] Subject: Is TESTCB a bad boy ? This message originated Externally. Use proper judgement and caution with attachments, links, or responses. In ancient times it was common practice to do this sort of thing... SWITCH NOP GO MVI SWITCH+1,X'F0' I believe this clears the cache and causes severe performance hits In my research into TESTCB for the z390 Project I found that it dynamically builds the subject instruction for an EX Would this have the same performance hit ? Melvyn Maltz. This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
