Here is how I code a similar instruction:
CNOP 2,4
LLILF R14,0
ORG *-4
DC A(symbol+X’80000000’)
BASSM R14,R15
So that the second operand can be an ADCON or VCON.
You could do the same with LRL.
Sent from my iPhone
> On May 4, 2021, at 9:18 AM, Peter Relson <[email protected]> wrote:
>
> Tony H asked about a use case for LRL:
> one obvious one is a non-reentrant module.
> Or, as Shmuel mentioned, it might have been needed for cases where there
> is no binder support for fullword immediate relocatable expressions.
>
> As to the OP's actual question, there are limited choices that come to
> mind
> -- the code was not actually running on a z10 or later machine; the OP
> says "not the case".
> -- If this is VM perhaps they have done something to ask that VM treat the
> execution environment as an older machine. There is the concept of the
> "virtual architecture level".
> -- the data shown does not represent what happened -- either it was not a
> PIC 1 or it was not a PIC 1 at that address. If this is repeatable then it
> could have been helpful to show some preceding data and have the trace
> that was shown cover the instruction before as well.
>
> Regardless, alignment of the operand is not relevant to the discussion. As
> pointed out, a misaligned operand would have resulted in a specification
> exception.
>
> Peter Relson
> z/OS Core Technology Design
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