I'd like to attempt to clear up some common misconceptions about the Relative Addressing instructions.
The "relative immediate" operand of the relative addressing instructions is a signed value representing a number of halfwords. The immediate operand value is effectively doubled and algebraically added to the address of the instruction (not the address contained in the PSW) to form a 64-bit intermediate address. A carry out of the most significant address bit is ignored. The intermediate address value is then modified according to the current addressing mode: - for 64-bit mode, all 64-bits are retained. - for 31-bit mode, bits 0 through 32 of the intermediate value are effectively set to zero. - for 24-bit mode, bits 0 through 39 of the intermediate value are effectively set to zero. For branch-type instructions when the branch is to be taken, this modified address value replaces the instruction address portion of the current PSW. There are other relative addressing instructions (for example, Load Relative Long) where the relative address calculation is used to obtain the address of an operand in storage. Similarly, for the Execute Relative Long instruction, the relative address calculation is used to obtain the address of a "target" instruction. When the target instruction itself uses relative addressing, the relative address calculations for the target instruction operands are performed as previously described, i.e., they are relative to the address of the target instruction, not the address of the Execute Relative Long instruction. This is all explained in detail in the z/Architecture Principles of Operation. Bob
