Thanks Seymour, it had never occurred to me they were totally identical apart
from CC and sign extension. I'd always had a suspicion that there might be
something that happened at the boundaries that I hadn't considered!
Good to know.
Best wishes / Mejores deseos / Meilleurs vœux
Ian ...
On Thursday, April 14, 2022, 04:31:29 PM GMT+2, Seymour J Metz
<[email protected]> wrote:
The S/360 architecture uses two's complement arithmetic, and that remains the
case through z. Accordingly, signed and unsigned arithmetic are the same except
for the condition code, except when sign extension is an issue, e.g., adding a
word to a grande register..
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
________________________________________
From: IBM Mainframe Assembler List [[email protected]] on behalf
of Ian Worthington [[email protected]]
Sent: Thursday, April 14, 2022 9:04 AM
To: [email protected]
Subject: Signed/unsigned operations
I noticed today that GCC generates for:
static __uint32_t sumu32; // unsigned int
static __uint64_t sumu64; // unsigned long
void addStuff(__uint64_t a64, __uint64_t b64, __uint32_t a32, __uint32_t b32 ) {
sumu32 = a32 + b32;
sumu64 = a64 + b64;
}
the following:
117: **** sumu32 = a32 + b32;
77 .loc 1 117 0
78 0044 5810B1C4 l %r1,452(%r11) # sumu32.6, a32
79 0048 5A10B1C0 a %r1,448(%r11) # sumu32.6, b32
80 004c C41F0000 strl %r1,sumu32 # sumu32.6, sumu32
80 0000
118: **** sumu64 = a64 + b64;
81 .loc 1 118 0
82 0052 E310B1D0 lg %r1,464(%r11) # sumu64.7, a64
82 0004
83 0058 E310B1C8 ag %r1,456(%r11) # sumu64.7, b64
83 0008
84 005e C41B0000 stgrl %r1,sumu64 # sumu64.7, sumu64
Have I grossly misunderstood something there? Can I really operate on an
unsigned integer with signed operations and get the correct results?
Best wishes / Mejores deseos / Meilleurs vœux
Ian ...
