Only if they are in the same cache line, which are 256 bytes the last I knew. ________________________________
Gary Weinhold Senior Application Architect DATAKINETICS | Data Performance & Optimization Phone:+1.613.523.5500 x216 Email: weinh...@dkl.com Visit us online at www.DKL.com E-mail Notification: The information contained in this email and any attachments is confidential and may be subject to copyright or other intellectual property protection. If you are not the intended recipient, you are not authorized to use or disclose this information, and we request that you notify us by reply mail or telephone and delete the original message from your mail system. From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> on behalf of Ngan, Robert (DXC Luxoft) <robert.n...@dxc.com> Sent: June 8, 2022 11:32 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU <ASSEMBLER-LIST@LISTSERV.UGA.EDU> Subject: Re: MVCRL Oops, didn't notice the "code is executing in getmained area" part. Doesn't that cause performance issues with Instruction/Data caches though? Robert Ngan DXC Luxoft -----Original Message----- From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> On Behalf Of Ngan, Robert (DXC Luxoft) Sent: Wednesday, June 8, 2022 10:17 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: MVCRL How would you gain relative access to a getmained area, other than by editing the immediate value in the instruction after the getmain? Robert Ngan DXC Luxoft -----Original Message----- From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> On Behalf Of Farley, Peter x23353 Sent: Tuesday, June 7, 2022 17:51 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: MVCRL Not if the code is executing in a getmained area. I've often put code in such areas for various reasons (e.g. OPEN exits, I/O error exits. etc.), and it's annoying to have to set up base registers. But I confess I think an "MVCRL" instruction where *both* source and destination are relative to the instruction address would see little use. If only the SOURCE address was relative to the instruction address, that might be a tad more useful. Then the D(L,B) for the destination could be in a reentrant area. Peter -----Original Message----- From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> On Behalf Of Ngan, Robert (DXC Luxoft) Sent: Tuesday, June 7, 2022 6:44 PM To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: Re: MVCRL If the source is relative to the instruction address, the code would most like be non-reentrant. Robert Ngan DXC Luxoft -----Original Message----- From: IBM Mainframe Assembler List <ASSEMBLER-LIST@LISTSERV.UGA.EDU> On Behalf Of Schmitt, Michael Sent: Tuesday, June 7, 2022 17:29 To: ASSEMBLER-LIST@LISTSERV.UGA.EDU Subject: MVCRL Why isn't there a Move Relative Long instruction, i.e. move with no registers, where both the source and destination are relative to the instruction address? Is this because there's no instruction format with two RI fields and a length? -- This message and any attachments are intended only for the use of the addressee and may contain information that is privileged and confidential. If the reader of the message is not the intended recipient or an authorized representative of the intended recipient, you are hereby notified that any dissemination of this communication is strictly prohibited. If you have received this communication in error, please notify us immediately by e-mail and delete the message and any attachments from your system.
