Tony,
I use this in TRAPPER in VSE:
VALID BEGIN=(R4),END=(R7),CHECK=READ
pretty obvious I guess
Martin
On 04.06.24 02:16, Tony Thigpen wrote:
Paul,
There is a major issue with just using CLC or OC to verify the
address, at least in my situation.
I can't just set up an exit to trap a soc4 (in my case, using a VSE
EXIT PC) because I am running within someone else's environment. They
may have already, such as in CICS, set up their own trap. That could
be damaging to the program calling my code.
Tony Thigpen
Paul Gilmartin wrote on 6/3/24 6:42 PM:
On 6/3/24 16:17, Tony Thigpen wrote:
I am also interested in the responses to the original question.
I provide a major subsystem with a very complex API on z/VSE.
(EZASMI/EZASOKET) One of our biggest issues is editing the addresses
passed in the parm list. While we have some code that seems to do
the required edits, it's not what I would call the best option. I am
watching this thread because something might be suggested that I can
also do on z/VSE.
I don't know what is behind the OPs question, but it is a good
question when you are a subsystem or called API and you have no
control over the caller's code and what they pass.
.
The hardware provides the control. If, like some complex instructions
which perform a test execution, you are concerned with preventing side
effects of a failure you can verify input parms are readable with
CLC parm,parm
and that output parms are writable with
OC parm,parm
There is some performance penalty and dump reading challenge.
--
gil
