On Sat, 23 Aug 2025 20:07:21 +0100, Rupert Reynolds <rupertreyno...@gmail.com> wrote:
>cater for the ever-evolving branch prediction, register renaming and stuff Be thankful, because other architectures than z have a far more complex pipeline. E.g. While most CPU's now offer out of order instruction processing, z doesn't need bells and whistles. The simplest bell and whistle involves the CPU being limited to 7 usable registers. The pipeline see's R1 being reused 3 times so these instruction sets can be run in parallel if they weren't using the same register. The pipeline would create 2 hidden registers to make this possible. z doesn't have this problem because of the instruction set design simplifies reuse. The z pipeline is 6 instructions and it's extremely unlikely a register will be reused in 6 instructions. Even if z had a 32 instruction pipeline, look at your code and see how often you reuse a register within 32 instructions. My guess is that it's rare.
