*Location:* *Chandler, AZ*

*Duration: 6+*

*Interview mode: phone then Skype*



*Job Description: *

The Verification Engineer is responsible for the verification of macro
blocks such USB (Universal Serial Bus) and MIPI M-.

The engineer will be involved in defining developing verification
components and building self-checking environments starting from written
specifications and in collaboration with others.

The engineer is also responsible for the verification of logic of IP
modules such as Application layer, ARM AXI/AHP/APB Bus interface, MAC and
PHY layer blocks etc.

The candidate is responsible for designing and coding constrained random
test benches and verification components using high level verification
language (HVL) such as SystemVerilog.

He/she will be developing test plans and test cases to meet the functional
and code coverage requirements.

The engineer should have good knowledge of OOP and verification
methodologies such as UVM or OVM or VMM.

The engineer should be familiar with design verification tools such as
Cadence IUS, or Synopsys DVE,

or Mentor Questa and will be performing logic simulations to ensure that
the design is thoroughly verified to meet the required specifications.

Should be fluent in the development of scripts and make files for
simulation regression automations and data qualification.



*Job/Education Requirements:          *

**BSEE (MSEE preferred). *

*Must be proficient in the development of verification components,
SystemVerilog, Verilog RTL, RTL simulation, pre & post silicon
verification.

*Should possess a good understanding of block and system level integration,
test and debug methodologies.

*Communicate well with others.

*Require 6+ years of experience in logic Verification and design validation.

Thank you
Regards

*Swami A *Sr. Marketer
Ennovace Inc
Ph: 214.541.9378
F: 724.264.5637
[email protected]


www.ennovace.com
1801 S O'connor Rd
Irving TX 75061

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