On 15 May 2005, at 17:26, Steve Underwood wrote:
Michael Welter wrote:
What is in the bug tracker helps make things clearer to people who know what they are doing. What we need is something that makes things clear to laymen. Saying internally and externally clocked doesn't cut it. It needs to be made clear to laymen that clocking internally is rarely right; that slaving to a PBX, when there is also a PSTN connection is almost never right; that the PSTN is the grand master of the telecoms universe, and all Asterisk boxes should be its slave.
Maybe the confusion is because some pieces of the explanation are being left out. If you look at the leads on a synchronous RS232 interface it is very clear: Rx clock and Tx clock, and people understand that. It's not as clear-cut with T1/E1.
I'm not the person to explain this, but someone (Rich Adamson perhaps, or a Digium engineer) needs to explain phase-locked loops and the recovery of the timing signal from the data stream. Perhaps understanding that the timing comes from the data stream itself might lead to better understanding.
Put the term PLL into an explanation, and 99% of the people reading will switch off.
I think of it in terms of cost of hardware. The most expensive kit generally has the
best clock source.
Make a list of all the devices that are talking to your T1/E1 cards, rank them in order of price - most expensive first.
99 times out of a 100 the one at the top should be use as the primary clock,
the next one down as secondary etc...
Regards, Steve
Tim.
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