Wen Gong <[email protected]> writes: >> -----Original Message----- >> From: ath10k <[email protected]> On Behalf Of Toke >> Høiland-Jørgensen >> Sent: Tuesday, August 20, 2019 8:24 PM >> To: Wen Gong <[email protected]>; [email protected] >> Cc: [email protected] >> Subject: [EXT] Re: [PATCH 4/7] ath10k: disable TX complete indication of htt >> for sdio >> >> Wen Gong <[email protected]> writes: >> >> > Tx complete message from firmware cost bus bandwidth of sdio, and bus >> > bandwidth is the bollteneck of throughput, it will effect the bandwidth >> > occupancy of data packet of TX and RX. >> > >> > This patch disable TX complete indication from firmware for htt data >> > packet, it results in significant performance improvement on TX path. >> >> Wait, how does that work? Am I understanding it correctly that this >> replaces a per-packet TX completion with a periodic one sent out of >> band? > When this patch applied, firmware will not indicate tx complete for tx > Data, it only indicate HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND, > This htt msg will tell how many data tx complete without status(status maybe > success/fail).
Ah, so this is basically a counter of how much data is currently queued in the firmware? >> And could you explain what the credits thing is for, please? :) > For high latency bus chip, all the tx data's content(include ip/udp/tcp header > and payload) will be transfer to firmware's memory via bus. > And firmware has limited memory for tx data, the tx data's content must > Saved in firmware memory before it tx complete, if ath10k transfer tx > data more than the limit, firmware will occur error. The credit is used > to avoid ath10k exceed the limit. What's a typical limit in the firmware? -Toke _______________________________________________ ath10k mailing list [email protected] http://lists.infradead.org/mailman/listinfo/ath10k
