2011/11/21 Adrian Chadd <[email protected]>: > .. replying to this after having not slept for > 24 hours, thanks to > being in transit between the US and Western Australia..
Ouch ! I've done that a lot lately, without traveling :P > On 20 November 2011 15:56, Nick Kossifidis <[email protected]> wrote: >> Since we dont read a snapshot of the interrupt >> registers it might be possible to get a new interrupt >> while reading them. In this case we should make sure >> that we clear all SISR bits we get from PISR. > > Just to be clear, you _shouldn't_ clear the secondary status mask bit > in the primary status register when you write back 1's to the primary > ISR. > Clear the bits that you read in the secondary status registers. If you > clear the relevant bit in the primary status register then you may > also skip perfectly valid interrupts. > > You don't need to check the secondary registers and the primary ISR > bits for consistency. Just read what I did in freebsd-head : > src/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c . it works fine. > > > Adrian > ACK, thanks for the update ! It's just that docs say nothing about when and how PISR gets updated so i tried to manually update it. -- GPG ID: 0xEE878588 As you read this post global entropy rises. Have Fun ;-) Nick _______________________________________________ ath5k-devel mailing list [email protected] https://lists.ath5k.org/mailman/listinfo/ath5k-devel
