Felix Fietkau wrote: > Almost all chips are using the same values in the initvals - the > exceptions seem to be the ones that have had ETSI compliance fix > attempts already. I'm pretty sure the new values (if adjusted for > different bands) would be fully compatible.
For most of the chips, adjusting AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ/5GHZ from the previous values to -60 is sufficient and the initvals don't need any changes to be compliant. For some chips, the change in the max. CCA threshold require adjustments in the minCCApwr_thr field - it is easier to do this via the initvals. This has been done for AR9485, AR9462 and AR9565 so far. AR9485: new value is -50 dB AR9565: new value is -92 dB AR9462: chain 0 : 2G: -91dB, 5G: -88dB chain 1 : 2G: -91dB, 5G: -90dB The SoC chips do not have any corresponding changes in minCCApwr_thr for the new CCA_MAX_GOOD_VAL. The only weird exception is AR9331 which has new minCCApwr_thr values in the internal PCOEM driver, but not in the SoC driver - not sure which one is correct. Sujith _______________________________________________ ath9k-devel mailing list ath9k-devel@lists.ath9k.org https://lists.ath9k.org/mailman/listinfo/ath9k-devel
