Skunk Wrote: > Was jitter even thought of as something to be designed around, before > everyone started telling you how good the SB sounded, or did you get > lucky to some extent?
No, SB2 was specifically designed for high clock precision and low jitter, and we took into account all the feedback we'd received over the years from audiophiles. Less-than-perfect clocking was one of the niggles that people had with SB1, so we wanted to address it. There are many ways to produce a clock: 1) Use an integrated AC97 (pc audio) chipset with it's own crystal attached. good: inexpensive, bad: poor DAC quality and can't do both 44.1 and 48 khz without resampling. Motherboards, sound cards, and tubular music players generally use these chips because they are extremely cheap. 2) Use a programmable PLL to generate the desired clock. (a PLL is a device that can be used, among other things, to convert one clock frequency to another). SLIMP3 and Squeezebox1 used a DSP chip from Micronas, which had this this hardware built-in to the chip. A single crystal oscillator was used to genereate the CPU clock as well as the audio clocks. You can also get PLL chips that can be configured to produce different frequencies. advantage: much flexibility to generate all sorts of clocks disadvantage: generally can't hit the target frequency very precisely unless it's a convenient multiple of the master clock, also jitter can be much higher than a simple crystal osciallator. 3) Use a separate crystal oscillator for each sample rate (or multiple of the sample rate) that you want to produce. This is what SB2 and SB3 use - there are two separate crystals running at 44.1 x 256 = 11.2896MHz and 48 x 256 = 12.2880 MHz. A 74hcu04 drives the crystals and sends the clock to the logic circuits which generrate the DAC and s/pdif interfaces. Advantage: highest precision and lowest jitter Disadvantage: higher cost and can't generate arbitrary clock frequencies Maintaining clock integrity through the logic, all the way from the osciallator to the s/pdif or DAC output is important too. Here we use a Xilinx CPLD implementing our own s/pdif transmitter design. I won't discuss how it works except that it is designed for minimal clock distortion. I have since tested several mods including reclocking the signal outside the xilinx with a discrete flip-flop and found that there was not significant room for improvement in the output clocking, but we may learn more once I get my hadns on some fancier test equipment. :) -- seanadams ------------------------------------------------------------------------ seanadams's Profile: http://forums.slimdevices.com/member.php?userid=3 View this thread: http://forums.slimdevices.com/showthread.php?t=21556 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
