snarlydwarf Wrote: > The catch is that there is no clock in that data. There isn't a > seperate line saying "okay, here comes the next bit!" which would get > rid of the jitter argument completely. And because even the crystals > that control timing are not -exactly- accurate, you can see errors > where it tries to derive a clock. If the sender is sending bits at > 44,100 bits per second, and the receiver's clock is just a slight bit > off at 44,098 bits per second, it is going to misread some.This isn't quite > correct. The receiver does not generate its own clock from an oscillator. It extracts the clock from the SPDIF signal coming from the transport.
What you have described is data errors. Jitter is not data errors. Jitter is variations in the timing between adjacent clock pulses. Sometimes jitter can be so bad that it causes data errors, but that's very unusual and is not what most people are concerned about in digital-to-analog converters. The problem that jitter creates in a DAC is additional noise at the analog output. A digital sample is meant to represent "Voltage = V(n) at time = T(n)" where n is the number of the sample within the sequence. Generally the samples are equally spaced in time, so that T(101) - T(100) is the same as T(1001) - T(1000). The samples are sent to the DAC in sequence at a constant rate, along with a clock signal with one upward pulse per sample. Like snarlydwarf described for the hard drive, the data for V(100) is sent slightly before the 100th clock pulse to make sure it reaches the DAC before the clock pulse. When the clock pulse arrives, BAM. The DAC reads the data on its input pins and immediately changes its output level to the voltage that matches V(100). It holds that value while the 101st data sample arrives, then switches the output to V(101) when the next (101st) clock pulse arrives. Then the output is filtered to "connect the dots" of the stair-step output voltage and make a smooth curve that matches the original wave that was captured by the analog-to-digital converter in the studio. That's great, and if the clock pulses really are equally spaced then you should perfectly reproduce the original wave (assuming the analog to digital converter also works perfectly). But what happens if there is jitter in the clock -- meaning that there is some variation in the time between clock pulses? Imagine the DAC is reproducing a signal that is rising an equal amount from one sample to the next. With a regularly spaced clock, you can draw a straight line through the corners of the stair-stepped output. However, what if one of the clock pulses arrives early? The DAC with switch to the next voltage level early, so one of the step corners will be shifted over to the left of the straight line. After the filter smooths out the corners, that section of the output signal will be slightly higher than it should be. So, for a rising signal, an early clock pulse results in output that is too high. A late clock pulse results in output that is too low. For a falling signal, the results are just the opposite. The end result is that "noise" in the timing of the clock pulses gets translated by the DAC into voltage noise in the output signal. Why is it especially a problem with SPDIF? well, the more noise that you pick up in the clock signal, the more jitter will result. Ideally, you'd like to generate the clock right next to the DAC so that you've got the least possible chance to pick up additional jitter. Then you can send the clock signal all the way back to the transport to tell it how fast to send out the data. The transport doesn't care about jitter, it's just moving bits from one place to another. The exact timing doesn't matter except at the DAC. But with SPDIF, the clock is supplied by the transport and sent over a coaxial cable along with the data, and then separated by the receiver and sent on to the DAC. There is plenty of opportunity to pick up jitter there. In an ideal world, the receiver would be able to filter the heck out of the clock signal it receives and restore it to exactly equally-spaced pulses. In the world of consumer audio, that doesn't seem to be the case, and jitter that comes from the transport or is induced by noise in the cable driver, the cable, or the receiver, arrives at the DAC and creates corresponding voltage noise in the output signal. I don't know whether the amount of jitter present in most systems is enough to produce measurable differences in the output voltage, or for that matter, discernable differences in the sound. However, what I've described above is the theory, and the mechanism by which jitter *can* cause problems in DAC (or ADC) circuits. -- John Stimson ------------------------------------------------------------------------ John Stimson's Profile: http://forums.slimdevices.com/member.php?userid=218 View this thread: http://forums.slimdevices.com/showthread.php?t=24616 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
