Robin Bowes;184814 Wrote: > > Now, in an ideal world, this wouldn't be a problem - the signal > received would have nice square edges and it would be easy to determine > precisely when each sample occurs and, hence, construct the clock > signal.
Not to go too far off the deep end here, but even if the transitions were infinitely steep and perfectly timed, it would be difficult to extract a clean clock. Due to zeroes having one fewer transition than ones, the receiving PLL will generate data-correlated jitter of its own as it drifts slightly between bits. Julian Dunn's "J-Test" paper describes how this works and how to reveal a receiver's worst-case behavior using a special square-wave signal, which is measured after the DAC. There are ways to minimize data correlated jitter by using an elaborate two-stage PLL, but even then it's still an analog circuit susceptible to noise. You could never do better than a local oscillator. Of course, in an _ideal_ world we would have perfect PLLs, so I guess it would be a non-issue. :) Incidentally, this test is what Stereophile and others use, and while it is a very clever test that can be performed without any exotic gear, it unfortunately has been applied far beyond its intended purpose. I've seen it used even to characterize devices that don't have s/pdif inputs! I suspect this is where the unfortunate, widely believed notion that "jitter is a number" comes from. -- seanadams ------------------------------------------------------------------------ seanadams's Profile: http://forums.slimdevices.com/member.php?userid=3 View this thread: http://forums.slimdevices.com/showthread.php?t=33146 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
