mswlogo;207198 Wrote: 
> That's a really good point I had not thought of that if you can match
> your internal clock to that average clock coming in over SPDIF (via
> PLL) you can get rid of jitter and not have a problem with drift.
> Unless the drift drifts :).
> 
> Thanks for explaining, that's probably what Meridian and other dejitter
> DACs do.

That's how essentially all DACs work.  The issue is how to construct an
stable clock from a jittery input, and it's not as easy as just PLL.  A
PLL will smooth out a lot of the junk, but some will remain.

What seems to me to be the best idea is the Lavry approach, where you
have a largish buffer clocked out by an adjustable local oscillator. 
When the buffer gets a little full you speed up the clock slightly,
when it gets close to empty you slow it down slightly.  According to
them that tiny adjustment happens once ever 10 seconds or so - totally
inaudible, and goodbye jitter.


-- 
opaqueice
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