AndyC_772;238566 Wrote: > > What I do find surprising is that anybody designs a DAC that uses the > SPDIF input as a timing reference rather that merely a source of bits. > I've spent some of my spare time this year designing a DAC - based > around the AK4396 as it happens - which makes no attempt to directly > recover a clock from the SPDIF input. Incoming edges are used merely to > identify where bits start and finish so they can be sampled correctly, > nothing more. So, it's an inherent property of the design that input > jitter makes no difference at all. >
How do you deal with buffer underrun/overflow due to differences in average clock rates between your DAC's oscillator and the source's? There's the rub, I think. -- opaqueice ------------------------------------------------------------------------ opaqueice's Profile: http://forums.slimdevices.com/member.php?userid=4234 View this thread: http://forums.slimdevices.com/showthread.php?t=33146 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/lists/listinfo/audiophiles
