DCtoDaylight;419925 Wrote: > There's a white paper describing the circuit in a bit more detail as > well: > > http://www.wadia.com/technology/technicalpapers/ > > As I guessed, part of the reason they're doing it this way, is to give > the DAC's more settling time. They're also claiming to get the full SNR > benefit of a correlated signal, which I'm not sure I agree with. I'll > have to think about that some more... > > FWIW, for your DAC design, adding DAC chips in parallel, and feeding > them the same data, does result in an improvement in SNR, without the > fancy delayed data. I recall at least one DAC design that used 32 chips > in parallel!
THanks for the link. I'll give it a look. Wadia are correct - the signals do not have to be correlated in order to achieve the noise reduction they claim. I'm not doing parallel DACs in my current design, although I am using the same DAC chips and fully balanced (2 chips per channel). I want to become successful with my first foray into this before I get really tricky and start laying down FPGAs and have to learn how to do digital filtering and cubic splines and such. -- wayne325 ------------------------------------------------------------------------ wayne325's Profile: http://forums.slimdevices.com/member.php?userid=29916 View this thread: http://forums.slimdevices.com/showthread.php?t=62747 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/mailman/listinfo/audiophiles
