Well, thank you for starting a new thread (I was a bit shy, to be honest).
So, the idea was : to include the A/D clock in the initially recorded data. This could allow all the intermediate "transports" to do just that : transport the initial data (and clock, thus) without adding anything to the stored data. Whatever the number of intermediate transports the data+clock would remain unchanged. In the end, the overall error would be the one introduced by the D/A process trying to imitate whatever timing error was initially recorded. Perhaps it's a naive point of view, but, from the data+clock integrity point of view this is probably the best option. :) -- Themis SB3 - North Star dac 192 - Cyrus 8xp - Sonus Faber Grand Piano Domus ------------------------------------------------------------------------ Themis's Profile: http://forums.slimdevices.com/member.php?userid=14700 View this thread: http://forums.slimdevices.com/showthread.php?t=71464 _______________________________________________ audiophiles mailing list [email protected] http://lists.slimdevices.com/mailman/listinfo/audiophiles
