Paulo Marques schrieb:
Hi, all
Some time ago I toyed with trying to build a super-optimizer for the
avr. The project didn't went very far, but it produced a few small bits
of code that I think are worth sharing.
Basically I was trying to produce functions to multiply an 8 bit value
by 8 bit constants with a 16 bit result in avr families without a mul
instruction.
Hi Paulo,
can your optimizer produce results for other arithmetic than multiplication?
For example to get a sequence for
R >>>= 2
where R is an 8-bit register and >>> stands for "rotate right".
There is a 5-insn sequence
SWAP R
LSL R
ADC R,Z
LSL R
ADC R,Z
where Z means "a register containing 0", i.e. >>> 2 is performed as
<<< 4
<<< 1
<<< 1
With MUL instruction there is
LDI U,64
MUL R,U
OR R0,R1
MOV R,R0
but that needs an upper register U and for avr-gcc the zero-register R1
must be cleared:
CLR Z
so that this sequence is not shorter but only slower. The question is
if there exists a shorter sequence and maybe your tool knows some magic
to give the answer?
Johann
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