Trying to find out why my XMega 128A1 keeps resetting I noticed this in the XMega Manual:
11.7.3 STATUS – Watchdog Status Register Bit 0 - SYNCBUSY When writing to the CTRL or WINCTRL registers, the WDT needs to be synchronized to the other clock domains. During synchronization the SYNCBUSY bit will be read as one. This bit is automatically cleared after the synchronization is finished. Synchronization will only take place when the ENABLE bit for the Watchdog Timer is set. I do not see where this clock domain synchronization is accounted for in avr/wdt.h wdt_enable(). Am I missing something? App Note AVR1321 for the RTC32 explains the cross clock domain issue, however it doesn't really say what happens in the Watchdog or the RTC case if things are not in sync. Seems like this would cause the watchdog to not be enabled at random times when wdt_enable() is used in the XMega parts. _______________________________________________ AVR-libc-dev mailing list AVR-libc-dev@nongnu.org https://lists.nongnu.org/mailman/listinfo/avr-libc-dev
