As S, Pitchumani wrote:
> Bit 0 - SYNCBUSY
> When writing to the CTRL or WINCTRL registers, the WDT needs to be
> synchronized to the other clock domains. During synchronization the
> SYNCBUSY bit will be read as one. This bit is automatically cleared after
> the synchronization is finished. Synchronization will only take place
> when the ENABLE bit for the Watchdog Timer is set.
I don't read any requirements out of this to wait until SYNCBUSY is
cleared before being allowed to execute a WDR instruction (which is
what your implementation does).
As I read it, SYNCBUSY only has informational value: it turns '1' by
the time the WEN ("the ENABLE bit") is set, until the watchdog has
synchronized, when it will go '0' again.
But I agree that the wording is not completely unambiguous. Anyway,
if one is required to wait until SYNCBUSY is '0' before executing a
WDR, I think the manual should very clearly state it that way.
--
cheers, Joerg .-.-. --... ...-- -.. . DL8DTL
http://www.sax.de/~joerg/
Never trust an operating system you don't have sources for. ;-)
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