This FAQ item says:
The solution is simple: writing a logical 1 to it requires only a
single OUT instruction, and it is clear that only this single
interrupt request bit will be cleared. There is no need to perform a
read-modify-write cycle (like, an SBI instruction), since all bits in
these control registers are interrupt bits, and writing a logical 0 to
the remaining bits (as it is done by the simple OUT instruction) will
not alter them, so there is no risk of any race condition that might
accidentally clear another interrupt request bit. So instead of
writing
TIFR |= _BV(TOV0); /* wrong! */
simply use
TIFR = _BV(TOV0);
The WDIF flag of WDTCSR appears to be a notable exception to this
advice. It coexists in WDTCSR with WDIE (watchdog interrupt enable),
so clearing it using the above method would probably have the
undesirable side effect of disabling watchdog interrupts (if enabled).
I haven't tested this yet but if correct it might deserve a mention in
this FAQ items, especially since the bit does use the "write 1 to
clear" mechanism. For this bit it looks like either a
read-modify-write must be used, or else a particular order of
operations observed in which WDIE is set as desired after the clear.
Either way the operation must probably be performed with interrupts
disabled.
Britton
