see 1st ur intent is not clear, u can't create a clock internally in ur design,of course for verification purpose u can create a clock,which is non-synthesizable. either u can divide or multiply ur main clock frequency.main clock refers either crystal oscillator or from the external world.
regards Raja.s On Tue, Oct 21, 2008 at 8:04 PM, vishnu pabbathi <[EMAIL PROTECTED]>wrote: > I am a student , i want verilog code for digital clock ,please send me any > one to my mail. > > > > -- thanks and regards raja.s +919789981883 Chennai --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "VLSI\ASIC\SoC Jobs(Bangalore Jobs)" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [EMAIL PROTECTED] For more options, visit this group at http://groups.google.com/group/bangalorechip -~----------~----~----~----~------~----~------~--~---
