Hi , Can u give u r mail address , i am not able forward my resume .
Regards ~Sampath On Nov 4, 2:12 pm, "Bangalorean VLSI" <[EMAIL PROTECTED]> wrote: > Hi, > > Please find the requirement. > > Mail Me back if it meets ur profile .... > > *Physical Design Engineer * > > Experience Level : 3 – 6 years > > Education : BE / BTech / ME / MTech > > Designation : Engineers / Senior Engineers > > Job Locations : Bangalore & Hyderabad > > No. of Positions : 20 + positions > > Skills : ** > > · Successful implementation of multimillion gate SoC designs in 45nm > & 65nm technologies (1M to 40M+ gates) / Netlist to GDSII capabilities > > · Work on all aspects of physical design including synthesis, floor > planning, place and route, clock distribution, IP integration, extraction, > timing closure, power and signal integrity analysis, physical verification, > DFM, and tapeout > > · Expertise in Synopsys, Magma or Cadence tools > > · Scripting using Tcl or Perl desirable > > *NOTE:* > > · Candidates must join on or before January 15, 2009· > > Thanks --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "VLSI\ASIC\SoC Jobs(Bangalore Jobs)" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [EMAIL PROTECTED] For more options, visit this group at http://groups.google.com/group/bangalorechip -~----------~----~----~----~------~----~------~--~---
