Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
---
 arch/arm/mach-imx/imx.c                       | 49 +++++++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/reset-reason.h | 17 ++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/mach-imx/include/mach/reset-reason.h

diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 9400105c6..e860e298a 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -14,8 +14,11 @@
 #include <common.h>
 #include <of.h>
 #include <init.h>
+#include <io.h>
 #include <mach/revision.h>
+#include <mach/reset-reason.h>
 #include <mach/generic.h>
+#include <reset_source.h>
 
 static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN;
 
@@ -147,3 +150,49 @@ static int imx_init(void)
        return ret;
 }
 postcore_initcall(imx_init);
+
+void imx_set_reset_reason(void __iomem *srsr)
+{
+       enum reset_src_type type = RESET_UKWN;
+       const u32 reg = readl(srsr);
+
+       /*
+        * SRSR register captures ALL reset event that occured since
+        * POR, so we need to clear it to make sure we only caputre
+        * the latest one.
+        */
+       writel(reg, srsr);
+
+       switch (reg) {
+       case IMX_SRC_SRSR_IPP_RESET: /* FALLTHROUGH */
+       case IMX_SRC_SRSR_IPP_RESET | IMX_SRC_SRSR_WDOG1_RESET:
+               type = RESET_POR;
+               break;
+       case IMX_SRC_SRSR_WDOG3_RESET: /* FALLTHROUGH */
+       case IMX_SRC_SRSR_WDOG4_RESET: /* FALLTHROUGH */
+       case IMX_SRC_SRSR_WDOG1_RESET:
+               type = RESET_WDG;
+               break;
+       case IMX_SRC_SRSR_JTAG_RESET: /* FALLTHROUGH */
+       case IMX_SRC_SRSR_JTAG_SW_RESET:
+               type = RESET_JTAG;
+               break;
+       case IMX_SRC_SRSR_TEMPSENSE_RESET:
+               type = RESET_THERM;
+               break;
+       case IMX_SRC_SRSR_WARM_BOOT:
+               type = RESET_RST;
+               break;
+       }
+
+       reset_source_set(type);
+
+       switch (reg) {
+       case IMX_SRC_SRSR_WDOG3_RESET:
+               reset_source_set_instance(type, 1);
+               break;
+       case IMX_SRC_SRSR_WDOG4_RESET:
+               reset_source_set_instance(type, 2);
+               break;
+       }
+}
diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h 
b/arch/arm/mach-imx/include/mach/reset-reason.h
new file mode 100644
index 000000000..96b905303
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/reset-reason.h
@@ -0,0 +1,17 @@
+#ifndef __MACH_RESET_REASON_H__
+#define __MACH_RESET_REASON_H__
+
+#define IMX_SRC_SRSR_IPP_RESET         BIT(0)
+#define IMX_SRC_SRSR_CSU_RESET         BIT(1)
+#define IMX_SRC_SRSR_IPP_USER_RESET    BIT(3)
+#define IMX_SRC_SRSR_WDOG1_RESET       BIT(4)
+#define IMX_SRC_SRSR_JTAG_RESET                BIT(5)
+#define IMX_SRC_SRSR_JTAG_SW_RESET     BIT(6)
+#define IMX_SRC_SRSR_WDOG3_RESET       BIT(7)
+#define IMX_SRC_SRSR_WDOG4_RESET       BIT(8)
+#define IMX_SRC_SRSR_TEMPSENSE_RESET   BIT(9)
+#define IMX_SRC_SRSR_WARM_BOOT         BIT(16)
+
+void imx_set_reset_reason(void __iomem *srsr);
+
+#endif /* __MACH_RESET_REASON_H__ */
-- 
2.14.3


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