On 9/18/2011, Aman said:
I read the Appendix-D of BBedit-10's manual that explains codeless
language modules. But wasn't able to understand what changes should i
make to this info.plist in VerilogHDL.bblm language module to make it
fold the begin-end blocks!
Aman,
The Verilog module is compiled code. It is not a codeless
language module.
You'll find an info.plist file in all BBEdit language modules,
and those info.plist files do have some similarities to codeless
language modules, but they're not the same thing.
Probably the best way to get folding support into the Verilog
module is to write to [email protected] and request it.
Seth
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