Please try this patch without the pm_qos patch to see if it helps. The Broadcom
wl driver does this during the setup.
Thanks,
Larry
====================
Index: wireless-testing/drivers/ssb/driver_pcicore.c
===================================================================
--- wireless-testing.orig/drivers/ssb/driver_pcicore.c
+++ wireless-testing/drivers/ssb/driver_pcicore.c
@@ -606,6 +606,12 @@ int ssb_pcicore_dev_irqvecs_enable(struc
tmp |= 0x8;
ssb_pcie_write(pc, 0x4, tmp);
}
+ if (pdev->id.revision == 1) {
+ /* DLLP Link Control register. */
+ tmp = ssb_pcie_read(pc, 0x100);
+ tmp |= 0x40;
+ ssb_pcie_write(pc, 0x100, tmp);
+ }
if (pdev->id.revision == 0) {
const u8 serdes_rx_device = 0x1F;
@@ -615,12 +621,19 @@ int ssb_pcicore_dev_irqvecs_enable(struc
6 /* CDR */, 0x0100);
ssb_pcie_mdio_write(pc, serdes_rx_device,
7 /* CDR BW */, 0x1466);
- } else if (pdev->id.revision == 1) {
- /* DLLP Link Control register. */
- tmp = ssb_pcie_read(pc, 0x100);
- tmp |= 0x40;
- ssb_pcie_write(pc, 0x100, tmp);
+ } else if (pdev->id.revision >= 3 && pdev->id.revision <= 5) {
+ /* DLLP Power Management Threshold */
+ tmp = ssb_pcie_read(pc, 0x128) & 0x00FF;
+ tmp |= 0x7200;
+ ssb_pcie_write(pc, 0x128, tmp);
+ /* TODO: PCIe serdes workaround */
+ /* TODO: PCIe ASPM Clock Request workaround */
+ } else {
+ /* TODO: PCIe Extend L1 Timer - for core rev 7 or 8 */
+ /* TODO: PCIe No PLL Down workaround - for core rev 3
or 4 */
+ writew(readw(bus->mmio + 0x80A) | 0x8000, bus->mmio +
0x80A);
}
+
}
pc->setup_done = 1;
out:
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