Eric Brombaugh wrote:
Philip Balister wrote:The Xilinx versus Altera is not ideal, but the FPGA configuration should be easy to move between the two FPGA's.Just curious - what's the driver in the choice between Xilinx and Altera? I've been using Xilinx for many years now and have been fairly happy with them. At a previous job though, my colleagues insisted that Altera was their preference. These days I don't know much about the differences.
I think Chris is surrounded by Altera guys at the moment and he is "conforming" :)
In any case, well written HDL should port between the two fairly seamlessly. I find Xilinx's tools to be fairly good at inference, so there's usually no need to instantiate vendor-specific features except in a top-level wrapper where I/O and clock management becomes critical.
On page 18 of the Spartan-3E User Guide there is this paragraph: Voltage ControlConsequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when
jumper JP9 is set for 2.5VCan someone explain this to me? How much of a problem is this, especially since we want to run bank 0 at 1.8 volts.
Philip
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