Chris R. Anderson wrote:
Beyond making sure the FPGA on the interface board puts out the correct
voltage levels, I wanted to start a discussion on exactly how we're
going to get a bitstream into the FPGA. Obviously, we'd like the
Beagleboard to be able to program the FPGA directly, but I think a good
backup plan would be to make sure the FPGA can be programmed independently.
I don't have a whole lot of experience developing FPGA programming
interfaces (I usually just stick a JTAG connector on the board),
however, the Cyclone III can be set up to use a dual JTAG/Active Serial
interface. From my perspective, that's a plus, as we can put a memory
chip in the AS chain that will automatically program the stored
bitstream into the FPGA on powerup. Also, the JTAG has a mode where a
microprocessor can download a bitstream into the FPGA from an external
memory location (e.g., you could have the bitstream stored on an SD Card
and program it through the OMAP3).
The catch to using the JTAG mode is that it requires dedicating 4 pins
on the expansion header to connect to the JTAG pins on the FPGA.
Obviously, we could make judicious use of Zero-Ohm resistors so that an
end user has the option of not using the JTAG programming (and
reclaiming those pins).
The big question I wanted to throw out there is: Is this a viable
method of programming the FPGA? Does anyone have any suggestions for
other/better options? I'd like to keep the AS method out there, as the
students will feel better if they can program the FPGA directly (i.e.,
they can still demonstrate that the board works and get an "A").
Good points - I agree that you'd really want to have multiple options
for configuring the FPGA. An off-board standard JTAG port for initial
hardware bringup is a necessity - you're not going to want to be copying
your bitstreams in via the OMAP while you're in the middle of debugging.
Also, by not having a JTAG port you may be missing out on some useful
debug tools - I don't know about Altera, but in the Xilinx world I find
the Chipscope realtime debug/control tool indispensable, and that only
works through JTAG.
Once that phase of development is past however it would be nice to have
the OMAP control the configuration and not require separate
configuration flash memory. That cuts the cost and increases
flexibility, allowing easy field updates with minor software overhead. I
like the way the USRP handles it - no on-board flash for configuration
and the FPGA gets loaded via the linux drivers to whatever file you
happen to point it at.
Eric
