On the board we're building, I've used the FPGA to wire the McSPI3 pins on the Beagleboard's expansion header directly to the ADC's SPI control port, as well as connecting the ADC's output bus to the DAC's input. I've also modified spidev_test.c slightly to let me peek and poke individual control registers on the ADC. This afternoon I was able to take these photos:
http://www.flickr.com/photos/37393...@n02/3633415075/ http://www.flickr.com/photos/37393...@n02/3634230430/ The signal path is: Function generator -> 40dB attenuator -> LFRX daughterboard -> ADC -> DAC -> LFTX daughterboard -> oscilloscope. I changed the following registers on the ADC: 2: 0x14 (set receive PGA gain to 20dB) 11: 0x48 (add offset current to output) 14: 0x80 (set current gain on TX channel to maximum) 16: 0xff (set transmit PGA gain to 0dB) You can see quite a bit of noise in the output and some distortion (?) around the zero crossings. These probably aren't even close to the optimal settings, but I thought I'd share some proof that something's working. The next step will be to get samples moving to and from the Beagle, probably using one SPI port for data and the other to control the ADC. I've attached the VHDL and C code I used for anyone interested. George Schaertl
peek-poke.c
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eastwood.vhd
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