Can you check the clock polarity and phase ?

This is always happen in my previous projects


2013/9/23 shedmeister <[email protected]>

> I've been battling this problem for over a month now.  I now have a
> concrete correlation that I can not ignore.  The problem occurs when the #
> of words I write to the TX FIFO exceeds 32 (the internal FIFO size).  I
> looked at the Sitara errata and there is no mention of SPI at all.  At his
> point I would settle for a workaround.  I can reset the transmit FIFO after
> each TX message goes out - is there a way to do this?
>
> Thanks,
>  Jim
>
>
> On Sunday, August 25, 2013 5:09:32 PM UTC-4, shedmeister wrote:
>>
>> I'm having an intermittent problem running the BBB's SPI1 in slave mode.
>>  I have designed all my TX messages to end in 0, and have verified every
>> way I know how that the last byte written to MCSPI_TX0 is 0.  But after a
>> few minutes of running, there is a non-zero value stuck on the output.  It
>> is usually 0x80, (I am in 8-bit mode), and I can clearly see the 0x80
>> coming out of the D1 line on a scope.  The communication is very reliable
>> initially, several messages get through OK before the error.  I have to
>> soft reset the BBB'S SPI to clear the error condition.
>>
>> Any ideas?
>>  Thanks,
>>   Jim
>>
>>
>>  --
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