Maybe is that because you have missed the start of the discussion, where 
I've said : 

(...)Therefore if you dig into the A8 arm documentation 
> CortexA_ProgGuide.pdf  that you can easily download from Arm website ( 
> free account is required) 


as the question was about Angstrom only, and I was refering to the Arm 
documentation you will find :

 

> *Floating-point code generation*

 

> *neon + hard = VFPv3 and Advanced SIMD code, where the floating-point and 
> SIMD types use the hardware FP registers
> *


>From my understanding Neon and vfp have a tight relationship, they even use 
the same registers. Anyway  the compiler 
is free to use any NEON or VFPv3 registers for floating-point values.

Nevertheless, I could eventually misunderstanding the documentation, please 
then let me know.


Le mercredi 30 octobre 2013 15:53:29 UTC+1, RobertCNelson a écrit :
>
> On Wed, Oct 30, 2013 at 9:42 AM, dlewin555 <[email protected]<javascript:>> 
> wrote: 
> > I think that it can be -at worst -ambiguous, not so wrong: let me resay 
> it : 
> > 
> > "Nevertheless,the only reference to the fp operation context switch cost 
> > I've found is related to the VFP which we don't use ONLY with the Sitara 
> > under Angstrom" as we are talking about hardfloat and softfloat , vfpv3 
> is 
> > not used as is ( read soft/softfp) . when hard for gcc option is used 
> this 
> > implies neon : then your code will be VFP3 and SIMD codes. 
> > Hope this is clearer. 
>
> "hard" with gcc doesn't actually imply neon either.. 
>
> 'armhf' in ubuntu/debian is actually built for "--with-fpu=vfpv3-d16 
> --with-float=hard --with-mode=thumb" which allows "non-neon" 
> implementations (such as the tegra2 and one marvel chip) to use it. 
>
> Whereas Angstrom for the beagle has always used the full floating 
> point resources as the omap/sitara parts from TI have the full 32 
> register vfpv3 with neon implementation.. 
>
> Regards, 
>
> -- 
> Robert Nelson 
> http://www.rcn-ee.com/ 
>

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