On Sun, Jan 5, 2014 at 9:10 PM, liyaoshi <[email protected]> wrote:

> Post it on
> http://e2e.ti.com/support/arm/sitara_arm/f/791/t/312683.aspx
>
>
Just to close the loop here. As clarified on E2E the configuration in U-Boot
is correct.


>
> 2014/1/5 Vaibhav Bedia <[email protected]>
>
>>  On Thu, Dec 26, 2013 at 9:49 PM, liyaoshi <[email protected]> wrote:
>>
>>> Hi all
>>>
>>> I review the code from
>>>
>>>
>>> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/include/asm/arch-am33xx/ddr_defs.h;h=2278358ab200ecc26fc7500e01b11268fe7d43f5;hb=HEAD#l29
>>>
>>> Here
>>> #define MT47H128M16RT25E_EMIF_SDCFG   0x41805332
>>>
>>>
>>> https://raw.github.com/CircuitCo/BeagleBone-RevA5/master/BeagleBone_revA5_SCH.pdf
>>>
>>> A5 board use 256M ddr2 with MT47H128M16 on 16bit
>>>
>>> And from
>>>
>>>
>>> http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR2/2Gb_DDR2.pdf
>>>
>>> 256M DDR2 only have 14 raw address
>>>
>>> Ti Reference manual say
>>>
>>> [image: 内嵌图片 1]
>>>  This 332 mean use 15 ROW
>>>
>>> It should be 0x418052d2
>>>
>>> right ?
>>>
>>> Why BB a5 board can run so stable ?
>>>
>>>
>> Now this is odd. Care to post it to
>> http://e2e.ti.com/support/arm/sitara_arm/default.aspx ?
>>
>>
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>
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