CPU Friday, January 31, 2014 5:57:32 PM UTC-5, Charles Steinkuehler wrote: > On 1/31/2014 12:38 PM, [email protected] wrote: > > > According to the TRM, the Time Base module on each of the PWM > > > subsystems is clocked directly from the cpu clock. That is, its being > > > clocked at a period of 1 nsec. > > > > Where exactly are you seeing this? Virtually nothing on the chip but > > the ARM cores and directly connected caches will be running at 1 GHz. > > > > I show the PWMSS to be clocked by the L4 interconnect clock (see section > > 15.1.2.2) with a maximum functional clock frequency of 100 MHz (15.1.2.3). > > > > The L4_PER domain the PWM units are all connected to is for "slow" > > peripherals. The L4_Fast domain used for the PRU is only 200 MHz, and > > I'd be surprised if you could configure the L4_PER clock to be over 100 > > MHz (but I haven't crawled through all the clock routing and power > > management logic to prove this). > > > > > It can be prescaled down to 1/128,for > > > a period of 128 nsecs. The period and the counter compare registers > > > are only 16 bits wide so the minimum PWM frequency is about 120 MHz. > > > Is that correct? > > > > Take all your GHz numbers and divide by 10 for the actual 100 Mhz clock > > frequency. > > > > -- > > Charles Steinkuehler > > [email protected]
On Friday, January 31, 2014 5:57:32 PM UTC-5, Charles Steinkuehler wrote: > On 1/31/2014 12:38 PM, [email protected] wrote: > > > According to the TRM, the Time Base module on each of the PWM > > > subsystems is clocked directly from the cpu clock. That is, its being > > > clocked at a period of 1 nsec. > > > > Where exactly are you seeing this? Virtually nothing on the chip but > > the ARM cores and directly connected caches will be running at 1 GHz. > > > > I show the PWMSS to be clocked by the L4 interconnect clock (see section > > 15.1.2.2) with a maximum functional clock frequency of 100 MHz (15.1.2.3). > > > > The L4_PER domain the PWM units are all connected to is for "slow" > > peripherals. The L4_Fast domain used for the PRU is only 200 MHz, and > > I'd be surprised if you could configure the L4_PER clock to be over 100 > > MHz (but I haven't crawled through all the clock routing and power > > management logic to prove this). > > > > > It can be prescaled down to 1/128,for > > > a period of 128 nsecs. The period and the counter compare registers > > > are only 16 bits wide so the minimum PWM frequency is about 120 MHz. > > > Is that correct? > > > > Take all your GHz numbers and divide by 10 for the actual 100 Mhz clock > > frequency. > > > > -- > > Charles Steinkuehler > > [email protected] Thank you for the reply Charles. That makes sense. The section in the TRM on the Time-Base submodule, 15.2.2.3, pp 2004 identifies the "CPU system clock" SYSCLKOUT as the source clock for the submodule. I'll use your information in my driver and test it with the hardware next week. Again, thanks for your information. Bob Stewart -- For more options, visit http://beagleboard.org/discuss --- You received this message because you are subscribed to the Google Groups "BeagleBoard" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/groups/opt_out.
